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Carlos Delfino 4 years ago committed by GitHub
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Projects/1-Beginner/RISCuinho-core.md
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@ -10,8 +10,7 @@ RISCuinho was synthesized using HDL Verilog and simulated with iVerilog, so for
* iVerilog Installed * iVerilog Installed
* GTKWave Installed * GTKWave Installed
The project is constantly expanding, and I'm working to add new extensions and tools. The project is constantly expanding, and I'm working to add new extensions and tools to supporting ones as a graphical interface for analyzing the simulation/synthesis.
the supporting ones as a graphical interface for analyzing the simulation/synthesis.
## User Stories ## User Stories

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