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Projects/1-Beginner/RISCuinho-core.md

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+# RISCuinho - Core
+
+**Tier:** 1-Beginner
+
+Simulates a core for microconcrolator with the extension RV32I of ISA RISC-V implemented in almost its entirety, its goal is to create a learning platform in advanced programming for microcontrollers, using from Assembly to C (not excluding other languages like Python).
+
+RISCuinho was synthesized using HDL Verilog and simulated with iVerilog, so for its study, testing and development the following tools are needed:
+
+* An editor that allows you to code as Vi, NotePad++, VsCode, preferably that has highlith syntax for Verilog (you can get plugins for Vi and Vs Code.
+* iVerilog Installed
+* GTKWave Installed
+
+The project is constantly expanding, and I'm working to add new extensions and tools to supporting ones as a graphical interface for analyzing the simulation/synthesis.
+
+## User Stories
+
+- Study assembly codes generated manually or by compilation of other languages.
+- Study and expand your knowledge in Hardware Synthesis, especially microcontrollers
+
+## Bonus features
+
+- It's an opportunity for new hardware projects breaking the Arduino or ESP32 paradigm
+
+## Useful links and resources
+
+The project has a website where I am slowly adding study material, descriptions of RISC-V Assembly instructions, tutorials for RISCuinho: https://riscuinho.github.io
+
+## Example projects
+
+There are several similar projects, but none have the proposal of a learning partnership and creating a Framework for studies, see the RISC-V Collection on GitHub Explore ](https://github.com/collections/riscv-cores).

Projects/2-Intermediate/SIMULinho.md

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+# SIMULinho
+
+**Tier:** 1-Intermediate
+
+The Project aims to create a graphical interface that controls the synthesis/simulation of a RISC-V microcontroller encoded using HDL Verilog. With this interface, Estudande will be able to visualize the internal processes of the microcontroller, such as changing registers, clock status of the main flags of the simulation, in addition to inserting and changing the data and program memory, so it will be able to insert new codes for tests quickly and simply .
+
+## Necessary resources
+
+To participate in the project, the student/maker needs to develop skills in software development using the C/C++ language and its entire universe, develop skills in the use of Qt5 in addition to the hardware synthesis tools related to Verilog language.
+
+## User Stories
+
+- SIMULinho is in the proof of concept phase
+
+## Bonus features
+
+Those involved will learn how to synthesize hardware using HDL Verilog, how to program in C/C++, Qt5 and integrate support code and analyze to iVerilog.
+
+
+## Useful links and resources
+
+- https://riscuinho.github.io
+
+## Example projects
+
+- https://riscuinho.github.io/venus/
+- https://riscuinho.github.io/emulsiV/

README.md

@@ -78,6 +78,7 @@ required to complete them.
 | [Wind Chill](./Projects/1-Beginner/Windchill-App.md)                              | Calculate the windchill factor from an actual temperature  | 1-Beginner |
 | [Word Frequency](./Projects/1-Beginner/Word-Frequency-App.md)                     | Calculate word frequency in a block of text                | 1-Beginner |
 | [Weather App](./Projects/1-Beginner/Weather-App.md)                               | Get the temperature, weather condition of a city.          | 1-Beginner |
+| [RISCuinho - Core](./Projects/1-Beginner/RISCuinho-core.md)                       | A Core RISC-v synthesized in Verilog, a scratch in the microcontroller universe. | 1-Beginner | 
 
 ### Tier-2: Intermediate Projects
 
@@ -116,6 +117,7 @@ required to complete them.
 | [To-Do App](./Projects/2-Intermediate/To-Do-App.md)                               | Manage personal to-do tasks                        | 2-Intermediate |
 | [Typing Practice](./Projects/2-Intermediate/Typing-Practice-App.md)               | Typing Practice                                    | 2-Intermediate |
 | [Voting App](./Projects/2-Intermediate/Voting-App.md)                             | Voting App                                         | 2-Intermediate |
+| [SIMULinho](./Projects/2-Intermediate/SIMULinho.md)                               | An interface to analyze and control simulation and synthesis with HDL Verilog for RISC-V microcontrollers like RISCuinho | 2-Intermediate |
 
 ### Tier-3: Advanced Projects